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HB52D328DC-B
256 MB Unbuffered SDRAM S.O.DIMM 32-Mword x 64-bit, 100 MHz Memory Bus, 2-Bank Module (8 pcs of 16 M x 16 components) PC100 SDRAM
E0084H10 (1st edition) (Previous ADE-203-1188A (Z)) Jan. 31, 2001 Description
The HB52D328DC is a 16M x 64 x 2 banks Synchronous Dynamic RAM Small Outline Dual In-line Memory Module (S.O.DIMM), mounted 8 pieces of 256-Mbit SDRAM (HM5225165BTT) sealed in TSOP package and 1 piece of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the product is 144pin Zig Zag Dual tabs socket type compact and thin package. Therefore, it makes high density mounting possible without surface mount technology. It provides common data inputs and outputs. Decoupling capacitors are mounted beside TSOP on the module board.
Features
* Fully compatible with : JEDEC standard outline 8-byte S.O.DIMM : Intel PCB Reference design (Rev.1.0) * 144-pin Zig Zag Dual tabs socket type (dual lead out) Outline: 67.60 mm (Length) x 31.75 mm (Height) x 3.80 mm (Thickness) Lead pitch: 0.80 mm * 3.3 V power supply * Clock frequency: 100 MHz (max) * LVTTL interface * Data bus width: x 64 Non parity * Single pulsed RAS * 4 Banks can operates simultaneously and independently * Burst read/write operation and burst read/single write operation capability * Programmable burst length : 1/2/4/8
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HB52D328DC-B
* 2 variations of burst sequence Sequential (BL = 1/2/4/8) interleave (BL = 1/2/4/8) * Programmable CE latency : 2/3 (HB52D328DC-A6B/A6BL) : 3 (HB52D328DC-B6B/B6BL) * Byte control by DQMB * Refresh cycles: 8192 refresh cycles/64 ms * 2 variations of refresh Auto refresh Self refresh * Low self refresh current: HB52D328DC-A6BL/B6BL (L-version)
Ordering Information
Type No. HB52D328DC-A6B HB52D328DC-B6B HB52D328DC-A6BL HB52D328DC-B6BL Frequency 100 MHz 100 MHz 100 MHz 100 MHz CE latency 2/3 3 2/3 3 Package Small outline DIMM (144-pin) Contact pad Gold
Data Sheet E0084H10
2
HB52D328DC-B
Pin Arrangement
Front Side
1pin 2pin
59pin 60pin
61pin 62pin
143pin 144pin
Back Side
Front side Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 Signal name Pin No. VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 VSS DQMB0 DQMB1 VCC A0 A1 A2 VSS DQ8 DQ9 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111
Back side Signal name Pin No. NC VSS NC NC VCC DQ16 DQ17 DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VCC A6 A8 VSS A9 A10 (AP) 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Signal name Pin No. VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 VSS DQMB4 DQMB5 VCC A3 A4 A5 VSS DQ40 DQ41 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 Signal name CK1 VSS NC NC VCC DQ48 DQ49 DQ50 DQ51 VSS DQ52 DQ53 DQ54 DQ55 VCC A7 BA0 VSS BA1 A11
Data Sheet E0084H10
3
HB52D328DC-B
Front side Pin No. 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 Signal name Pin No. DQ10 DQ11 VCC DQ12 DQ13 DQ14 DQ15 VSS NC NC CK0 VCC RE W S0 S1 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 Back side Signal name Pin No. VCC DQMB2 DQMB3 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS SDA VCC 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 Signal name Pin No. DQ42 DQ43 VCC DQ44 DQ45 DQ46 DQ47 VSS NC NC CKE0 VCC CE CKE1 A12 NC 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 Signal name VCC DQMB6 DQMB7 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS SCL VCC
Data Sheet E0084H10
4
HB52D328DC-B
Pin Description
Pin name A0 to A12 Function Address input Row address Column address BA0/BA1 DQ0 to DQ63 S0/S1 RE CE W DQMB0 to DQMB7 CK0/CK1 CKE0/CKE1 SDA SCL VCC VSS NC Bank select address Data-input/output Chip select Row address asserted bank enable Column address asserted Write enable Byte input/output mask Clock input Clock enable Data-input/output for serial PD Clock input for serial PD Power supply Ground No connection A0 to A12 A0 to A8
Data Sheet E0084H10
5
HB52D328DC-B
Serial PD Matrix*1
Byte No. Function described 0 1 2 3 4 5 6 7 8 9 Number of bytes used by module manufacturer Total SPD memory size Memory type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 80 08 04 0D 09 02 40 00 01 A0 128 256 byte SDRAM 13 9 2 64 0 (+) LVTTL CL = 3
Number of row addresses bits 0 Number of column addresses bits Number of banks Module data width 0 0 0
Module data width (continued) 0 Module interface signal levels 0 SDRAM cycle time (highest CE latency) 10 ns SDRAM access from Clock (highest CE latency) 6 ns Module configuration type Refresh rate/type 1
10
0
1
1
0
0
0
0
0
60
11 12
0 1
0 0
0 0
0 0
0 0
0 0
0 1
0 0
00 82
Non parity Normal (7.8125 s) Self refresh 16M x 16 -- 1 CLK
13 14 15
SDRAM width Error checking SDRAM width
0 0
0 0 0
0 0 0
1 0 0
0 0 0
0 0 0
0 0 0
0 0 1
10 00 01
0 SDRAM device attributes: minimum clock delay for backto-back random column addresses SDRAM device attributes: Burst lengths supported SDRAM device attributes: number of banks on SDRAM device SDRAM device attributes: CE latency SDRAM device attributes: S latency 0 0
16 17
0 0
0 0
0 0
1 0
1 1
1 0
1 0
0F 04
1, 2, 4, 8 4
18 19
0 0
0 0
0 0
0 0
0 0
1 0
1 0
0 1
06 01
2, 3 0
Data Sheet E0084H10
6
HB52D328DC-B
Byte No. Function described 20 21 22 23 SDRAM device attributes: W latency SDRAM module attributes SDRAM device attributes: General SDRAM cycle time (2nd highest CE latency) (-A6B/A6BL) 10 ns (-B6B/B6BL) 15 ns 24 SDRAM access from Clock (2nd highest CE latency) (-A6B/A6BL) 6 ns (-B6B/B6BL) 9 ns 25 SDRAM cycle time (3rd highest CE latency) Undefined SDRAM access from Clock (3rd highest CE latency) Undefined Minimum row precharge time Row active to row active min RE to CE delay min Minimum RE pulse width Density of each bank on module Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 01 00 0E A0 0 Non buffer VCC 10% CL = 2
1 0
1 1
1 1
1 0
0 0
0 0
0 0
0 0
F0 60 CL = 2
1 0
0 0
0 0
1 0
0 0
0 0
0 0
0 0
90 00
26
0
0
0
0
0
0
0
0
00
27 28 29 30 31 32 33 34 35
0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x
0 0 0 1 1 1 0 1 0 0 0 1 1 0 0 x
1 1 1 1 0 0 1 0 1 0 1 0 0 0 0 x
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x
1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 x
0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 x
0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 x
14 14 14 32 20 20 10 20 10 00 12 A1 21 07 00 xx
20 ns 20 ns 20 ns 50 ns 2 bank 128M byte 2 ns 1 ns 2 ns 1 ns Future use Rev. 1.2B 161 33 HITACHI
Address and command signal 0 input setup time Address and command signal 0 input hold time Data signal input setup time Data signal input hold time 0 0 0 0 1 0 0 0 x
36 to 61 Superset information 62 63 SPD data revision code Checksum for bytes 0 to 62 (-A6B/A6BL) (-B6B/B6BL) 64 Manuf act urer's JEDEC ID c ode
65 to 71 Manuf act urer's JEDEC ID c ode 72 Manufacturing location
* 3 (ASCII8bit code)
Data Sheet E0084H10
7
HB52D328DC-B
Byte No. Function described 73 74 75 76 77 78 79 80 81 82 83 84 Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number (-A6B/A6BL) (-B6B/B6BL) 85 86 87 Manufacturer's part number Manufacturer's part number Manufacturer's part number (L-version) Manufacturer's part number 88 89 90 91 92 93 94 Manufacturer's part number Manufacturer's part number Manufacturer's part number Revision code Revision code Manufacturing date Manufacturing date Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x *6 -- 0 -- 1 1 -- 1 0 -- 0 0 -- 0 1 -- 1 1 -- 0 1 -- 0 1 -- 64 CF *5 100 MHz CL = 2, 3 1 1 0 0 1 0 0 0 1 1 0 1 1 0 1 1 0 0 0 0 0 0 x x 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 0 1 1 1 1 1 1 x x 0 0 1 1 0 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 x x 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 x x 0 0 1 0 1 0 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 x x 0 1 0 1 0 1 1 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 x x 0 0 1 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 x x 48 42 35 32 44 33 32 38 44 43 2D 41 42 36 42 4C 20 20 20 20 30 20 xx xx H B 5 2 D 3 2 8 D C -- A B 6 B L (Space) (Space) (Space) (Space) Initial (Space) Year code (BCD)*4 Week code (BCD)*4
95 to 98 Assembly serial number 99 to 125 Manufacturer specific data 126 127 Intel specification frequency
Intel specification CE# latency 1 support (-A6B/A6BL) (-B6B/B6BL) 1
1
0
0
1
1
0
1
CD
CL = 3
Data Sheet E0084H10
8
HB52D328DC-B
Notes: 1. All serial PD data are not protected. 0: Serial data, "driven Low", 1: Serial data, "driven High" These SPD are based on Intel specification (Rev.1.2B). 2. Regarding byte32 to 35, based on JEDEC Committee Ballot JC42.5-97-119. 3. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows "J" on ASCII code.) 4. Regarding byte93 and 94, based on JEDEC Committee Ballot JC42.5-97-135. BCD is "Binary Coded Decimal". 5. All bits of 99 through 125 are not defined ("1" or "0"). 6. Bytes 95 through 98 are assembly serial number.
Data Sheet E0084H10
9
HB52D328DC-B
Block Diagram
W S1 S0 DQMB0 8 N0, N1 DQ0 to DQ7 DQMB4 8 N2, N3 DQ32 to DQ39 DQMB1 8 N4, N5 DQ8 to DQ15 DQMB5 8 N6, N7 DQ40 to DQ47 RE CE A0 to A12 BA0 BA1 CKE0 CKE1 CK0 CK1 VCC
C100-C123
CS
CS
DQMB2 8 N8, N9
CS
CS
D0
D4
DQ16 to DQ23 DQMB6 8 N10, N11 DQ48 to DQ55
D2
D6
CS
CS
DQMB3 8 N12, N13
CS
CS
D1
D5
DQ24 to DQ31 DQMB7 8 N14, N15 DQ56 to DQ63
D3
D7
RAS (D0 to D7) CAS (D0 to D7) A0 to A12 (D0 to D7) A13 (D0 to D7) A12 (D0 to D7) CKE (D0 to D3) CKE (D4 to D7) CLK (D0 to D3) CLK (D4 to D7) VCC (D0 to D7, U0) VSS (D0 to D7, U0) SCL
Serial PD SCL A0 A1 A2 VSS Notes : 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state. * D0 to D7 : HM5225165 U0 : 2-kbit EEPROM C100 to C123 : 0.1 F N0 to N15 : Network resistors (10 ) U0 SDA SDA
VSS
Data Sheet E0084H10
10
HB52D328DC-B
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Note: 1. Respect to V SS . Symbol VT VCC Iout PT Topr Tstg Value -0.5 to VCC + 0.5 ( 4.6 (max)) -0.5 to +4.6 50 4.0 0 to +65 -55 to +125 Unit V V mA W C C Note 1 1
DC Operating Conditions (Ta = 0 to +65C)
Parameter Supply voltage Symbol VCC VSS Input high voltage Input low voltage Notes: 1. 2. 3. 4. 5. VIH VIL Min 3.0 0 2.0 -0.3 Max 3.6 0 VCC + 0.3 0.8 Unit V V V V Notes 1, 2 3 1, 4 1, 5
All voltage referred to VSS The supply voltage with all VCC pins must be on the same level. The supply voltage with all V SS pins must be on the same level. VIH (max) = VCC + 2.0 V for pulse width 3 ns at VCC. VIL (min) = VSS - 2.0 V for pulse width 3 ns at VSS .
Data Sheet E0084H10
11
HB52D328DC-B
VIL/VIH Clamp (Component characteristic)
This SDRAM component has VIL and V IH clamp for CK, CKE, S, DQMB and DQ pins. Minimum VIL Clamp Current
VIL (V) -2 -1.8 -1.6 -1.4 -1.2 -1 -0.9 -0.8 -0.6 -0.4 -0.2 0 I (mA) -32 -25 -19 -13 -8 -4 -2 -0.6 0 0 0 0
0 -2 -5 -10 I (mA) -15 -20 -25 -30 -35
-1.5
-1
-0.5
0
VIL (V)
Data Sheet E0084H10
12
HB52D328DC-B
Minimum VIH Clamp Current
VIH (V) VCC + 2 VCC + 1.8 VCC + 1.6 VCC + 1.4 VCC + 1.2 VCC + 1 VCC + 0.8 VCC + 0.6 VCC + 0.4 VCC + 0.2 VCC + 0 I (mA) 10 8 5.5 3.5 1.5 0.3 0 0 0 0 0
10 8 I (mA) 6 4 2 0 VCC + 0 VCC + 0.5 VCC + 1 VIH (V) VCC + 1.5 VCC + 2
Data Sheet E0084H10
13
HB52D328DC-B
IOL/IOH Characteristics (Component characteristic)
Output Low Current (IOL)
I OL Vout (V) 0 0.4 0.65 0.85 1 1.4 1.5 1.65 1.8 1.95 3 3.45 Min (mA) 0 27 41 51 58 70 72 75 77 77 80 81 I OL Max (mA) 0 71 108 134 151 188 194 203 209 212 220 223
250
200 IOL (mA)
150 min max 100
50
0 0 0.5 1 1.5 2 Vout (V) 2.5 3 3.5
Data Sheet E0084H10
14
HB52D328DC-B
Output High Current (I OH ) (Ta = 0 to 65C, V CC = 3.0 V to 3.45 V, VSS = 0 V)
I OH Vout (V) 3.45 3.3 3 2.6 2.4 2 1.8 1.65 1.5 1.4 1 0 Min (mA) -- -- 0 -21 -34 -59 -67 -73 -78 -81 -89 -93 I OH Max (mA) -3 -28 -75 -130 -154 -197 -227 -248 -270 -285 -345 -503
0
0
0.5
1
1.5
2
2.5
3
3.5
-100
IOH (mA)
-200 min -300 max
-400
-500
-600 Vout (V)
Data Sheet E0084H10
15
HB52D328DC-B
DC Characteristics (Ta = 0 to 65C, VCC = 3.3 V 0.3 V, VSS = 0 V)
HB52D328DC -A6B/B6B/A6BL/B6BL Parameter Operating current (CE latency = 2) (CE latency = 3) Symbol Min I CC1 I CC1 -- -- -- -- -- -- -- Max 520 520 24 16 160 32 240 Unit mA mA mA mA mA mA mA CKE = VIL, t CK = 12 ns CKE = VIL, CK0/CK1 = VIL or VIH Fixed CKE, S = VIH, t CK = 12 ns CKE = VIH, t CK = 12 ns CKE, S = VIH, t CK = 12 ns t CK = min, BL = 4 6 7 4 1, 2, 6 1, 2, 4 Test conditions Burst length = 1 t RC = min Notes 1, 2, 3
Standby current in power down I CC2P Standby current in power down I CC2PS (input signal stable) Standby current in non power down I CC2N
Active standby current in power I CC3P down Active standby current in non power down Burst operating current (CE latency = 2) (CE latency = 3) Refresh current Self refresh current Self refresh current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage I CC3N
I CC4 I CC4 I CC5 I CC6 I CC6 I LI I LO VOH VOL
-- -- -- -- -- -10 -10 2.4 --
560 560 1000 24 16 10 10 -- 0.4
mA mA mA mA mA A A V V
1, 2, 5
t RC = min VIH VCC - 0.2 V VIL 0.2 V
3 8
0 Vin VCC 0 Vout VCC DQ = disable I OH = -4 mA I OL = 4 mA
Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CK0/CK1 operating current. 7. After power down mode, no CK0/CK1 operating current. 8. After self refresh mode set, self refresh current.
Data Sheet E0084H10
16
HB52D328DC-B
Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V)
Parameter Input capacitance (Address) Input capacitance (RE, CE, W, CK0/CK1, CKE0) Input capacitance (S0/S1) Input capacitance (DQMB) Input/Output capacitance (DQ) Notes: 1. 2. 3. 4. Symbol CIN CIN CIN CIN CI/O Max 60 60 40 30 27 Unit pF pF pF pF pF Notes 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 3, 4
Capacitance measured with Boonton Meter or effective capacitance measuring method. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing. DQMB = VIH to disable Data-out. This parameter is sampled and not 100% tested.
Data Sheet E0084H10
17
HB52D328DC-B
AC Characteristics (Ta = 0 to 65C, VCC = 3.3 V 0.3 V, VSS = 0 V)
HB52D328DC -A6B/B6B/A6BL/B6BL Parameter System clock cycle time (CE latency = 2) (CE latency = 3) CK high pulse width CK low pulse width Access time from CK (CE latency = 2) (CE latency = 3) Data-out hold time CK to Data-out low impedance CK to Data-out high impedance Data-in setup time Data in hold time Address setup time Address hold time CKE setup time Symbol t CK t CK t CKH t CKL t AC t AC t OH t LZ t HZ t DS t DH t AS t AH t CES Tsi Thi Tsi Thi Tsi Tpde Thi Tsi Thi Trc Tras Trcd Trp Tdpl Trrd PC100 Symbol Tclk Tclk Tch Tcl Tac Tac Toh Min 10 10 3 3 -- -- 3 2 -- 2 1 2 1 2 2 1 2 1 70 50 20 20 20 20 1 -- Max -- -- -- -- 6 6 -- -- 6 -- -- -- -- -- -- -- -- -- -- 120000 -- -- -- -- 5 64 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 1, 2 1, 2, 3 1, 4 1 1 1 1 1, 5 1 1 1 1 1 1 1 1 1 1 1 1 1, 2 Notes 1
CKE setup time for power down exit t CESP CKE hold time Command setup time Command hold time Ref/Active to Ref/Active command period Active to precharge command period Active command to column command (same bank) Precharge to active command period Write recovery or data-in to precharge lead time Active (a) to Active (b) command period Transition time (rise to fall) Refresh period t CEH t CS t CH t RC t RAS t RCD t RP t DPL t RRD tT t REF
Data Sheet E0084H10
18
HB52D328DC-B
Notes: 1. 2. 3. 4. 5. AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V. Access time is measured at 1.5 V. Load condition is C L = 50 pF. t LZ (max) defines the time at which the outputs achieves the low impedance state. t HZ (max) defines the time at which the outputs achieves the high impedance state. t CES defines CKE setup time to CK rising edge except power down exit command.
Test Conditions * Input and output timing reference levels: 1.5 V * Input waveform and output load: See following figures
2.4 V
input
0.4 V
2.0 V 0.8 V
DQ CL t
T
tT
Data Sheet E0084H10
19
HB52D328DC-B
Relationship Between Frequency and Minimum Latency
HB52D328DC Parameter Frequency (MHz) tCK (ns) Active command to column command (same bank) Active command to active command (same bank) Active command to precharge command (same bank) Precharge command to active command (same bank) Write recovery or data-in to precharge command (same bank) Active command to active command (different bank) Self refresh exit time Last data in to active command (Auto precharge, same bank) Self refresh exit to command input Precharge command to high impedance (CE latency = 2) (CE latency = 3) Last data out to active command (auto precharge) (same bank) Last data out to precharge (early precharge) (CE latency = 2) (CE latency = 3) Column command to column command Write command to data in latency DQMB to data in DQMB to data out CKE to CK disable Register set to active command S to command disable Power down exit to command input -A6B/B6B/A6BL/B6BL 100 PC100 Symbol Symbol 10 I RCD I RC I RAS I RP I DPL I RRD I SREX I APW I SEC Tsrx Tdal Tdpl 2 7 5 2 2 2 1 4 7 Notes 1 = [IRAS + IRP] 1 1 1 1 1 2 = [IDPL + IRP] = [IRC] 3
I HZP I HZP I APR
Troh Troh
2 3 1
I EP I EP I CCD I WCD I DID I DOD I CLE I RSA I CDD I PEC Tccd Tdwd Tdqm Tdqz Tcke Tmrd
-1 -2 1 0 0 2 1 1 0 1
Data Sheet E0084H10
20
HB52D328DC-B
Notes: 1. I RCD to IRRD are recommended value. 2. Be valid [DSEL] or [NOP] at next command of self refresh exit. 3. Except [DSEL] and [NOP]
Data Sheet E0084H10
21
HB52D328DC-B
Pin Functions
CK0/CK1 (input pin): CK is the master clock input to this pin. The other input signals are referred at CK rising edge. S0/S1 (input pin): When S is Low, the command input cycle becomes valid. When S is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RE, CE and W (input pins): Although these pin names are the same as those of conventional DRAM modules, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active command cycle CK rising edge. Column address (AY0 to AY8) is determined by A0 to A8 level at the read or write command cycle CK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, both banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0/BA1 (BA) is precharged. BA0/BA1 (input pin): BA0/BA1 is a bank select signal (BA). The memory array is divided into bank0, bank1, bank2 and bank3. If BA0 is Low and BA1 is Low, bank0 is selected. If BA0 is High and BA1 is Low, bank1 is selected. If BA0 is Low and BA1 is High, bank2 is selected. If BA0 is High and BA1 is HIgh, bank3 is selected. CKE0, CKE1 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for powerdown mode, clock suspend mode and self refresh mode. DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If the DQMB is Low, the output buffer becomes Low-Z (The latency of DQMB during reading is 2 clocks). Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low, the data is written (The latency of DQMB during writing is 0 clock). DQ0 to DQ63 (DQ pins): Data is input to and output from these pins. VCC (power supply pins): 3.3 V is applied. VSS (power supply pins): Ground is connected.
Detailed Operation Part
Refer to the HM5225165B/HM5225805B/HM5225405B-75/A6/B6 datasheet.
Data Sheet E0084H10
22
HB52D328DC-B
Physical Outline
Unit: mm inch 63.60 2.504 (Datum -A-) 3.80 Max 0.150 Max 2R3.00 Min 2R0.118 Min 3.20 Min 0.126 Min 4.00 Min 0.157 Min 1.00 0.10 0.039 0.004 (DATUM -A-) 0.60 0.05 0.024 0.002 0.25 Max 0.010 Max 4.00 0.10 0.157 0.004 0.100 Min 2.55 Min 2.5 0.098 R0.75 R0.030 1.50 0.10 0.059 0.004 DD380125W
67.60 2.661 24.50 0.965
31.75 1.250 6.00 0.236
3.30 0.130
23.20 0.913 2.50 0.098 2.10 0.083 23.20 0.913
2
B 4.60 0.181
32.80 1.291
A
2- o1.80 2- o0.071 2-R2.00 2-R0.079
Component area (back)
(Datum -A-)
2.00 Min 0.079 Min
Detail A
Detail B
0.80 0.031
Data Sheet E0084H10
23
4.00 0.10 0.157 0.004
3.70 0.146
4.60 0.181 32.80 1.291
144
143
1
20.00 0.787
Component area (front)
HB52D328DC-B
Cautions
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.'s or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products.
Data Sheet E0084H10
24

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